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| SPI42N03S2L-13 SPP42N03S2L-13 SPB42N03S2L-13 OptiMOS(R) Power-Transistor Features * N-channel * Enhancement mode * Logic level * Excellent gate charge x R DS(on) product (FOM) * Superior thermal resistance * 175 C operating temperature * Avalanche rated * dv /dt rated P-TO262-3-1 Product Summary V DS R DS(on),max ID 30 12.9 42 V m A P-TO263-3-2 P-TO220-3-1 Type SPP42N03S2L-13 SPB42N03S2L-13 SPI42N03S2L-13 Package P-TO220-3-1 P-TO263-3-2 P-TO262-3-1 Ordering Code Q67042-S4034 Q67042-S4035 Q67042-S4104 Marking 2N03L13 2N03L13 2N03L13 Maximum ratings, at T j=25 C, unless otherwise specified Parameter Continuous drain current1) Symbol Conditions ID T C=25 C T C=100 C Pulsed drain current Avalanche energy, single pulse Repetitive avalanche energy Reverse diode dv /dt Gate source voltage Power dissipation Operating and storage temperature IEC climatic category; DIN IEC 68-1 I D,pulse E AS E AR dv /dt V GS P tot T j, T stg T C=25 C T C=25 C I D=42 A, R GS=25 limited by T jmax 2) I D=42 A, V DS=24 V, di /dt =200 A/s, T j,max=175 C Value 42 42 248 110 8 6 20 83 -55 ... 175 55/175/56 mJ mJ kV/s V W C Unit A Rev. 2.0 page 1 2004-06-04 SPI42N03S2L-13 SPP42N03S2L-13 Parameter Symbol Conditions min. Thermal characteristics Thermal resistance, junction - case SMD version, device on PCB R thJC R thJA minimal footprint 6 cm2 cooling area3) Electrical characteristics, at T j=25 C, unless otherwise specified Static characteristics Drain-source breakdown voltage Gate threshold voltage Zero gate voltage drain current V (BR)DSS V GS=0 V, I D=1 mA V GS(th) I DSS V DS=V GS, I D=37 A V DS=30 V, V GS=0 V, T j=25 C V DS=30 V, V GS=0 V, T j=125 C Gate-source leakage current Drain-source on-state resistance4) I GSS R DS(on) V GS=20 V, V DS=0 V V GS=4.5 V, I D=21 A V GS=4.5 V, I D=21 A, SMD version V GS=10 V, I D=21 A V GS=10 V, I D=21 A, SMD version Gate resistance Transconductance RG g fs |V DS|>2|I D|R DS(on)max, I D=42 A 30 1.2 1.6 0.01 2 1 A V 1.2 1.8 62 40 K/W SPB42N03S2L-13 Unit max. Values typ. 21 10 1 14.9 14.5 10.3 9.9 1 42 100 100 19.9 19.6 12.9 12.6 S nA m 1) Current is limited by bondwire; with an R thJC=1.8 K/W the chip is able to carry 64 A at 25C, for detailed information see app.-note ANPS071E at www.infineon.com/optimos. 2) 3) Defined by design. Not subject to production test. Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm 2 (one layer, 70 m thick) copper area for drain connection. PCB is vertical in still air. 4) Diagrams are related to straight lead versions. Rev. 2.0 page 2 2004-06-04 SPI42N03S2L-13 SPP42N03S2L-13 Parameter Symbol Conditions min. Dynamic characteristics Input capacitance Output capacitance Reverse transfer capacitance Turn-on delay time Rise time Turn-off delay time Fall time Gate Charge Characteristics Gate to source charge Gate to drain charge Gate charge total Gate plateau voltage Reverse Diode Diode continous forward current Diode pulse current Diode forward voltage IS I S,pulse V SD T C=25 C V GS=0 V, I F=42 A, T j=25 C 0.95 42 248 1.25 V A Q gs Q gd Qg V plateau V DD=24 V, I D=21 A, V GS=0 to 10 V 2.7 7.9 22.9 3.5 3.6 11.9 30.5 V nC C iss C oss Crss t d(on) tr t d(off) tf V DD=15 V, V GS=10 V, I D=21 A, R G=7.8 V GS=0 V, V DS=25 V, f =1 MHz 850 330 90 6.5 12 24 14.5 1130 440 130 9.8 18 36 21.8 ns pF SPB42N03S2L-13 Unit max. Values typ. Reverse recovery time t rr V R=15 V, I F=I S, di F/dt =100 A/s - 24 31 ns Reverse recovery charge Q rr - 18 23 nC Rev. 2.0 page 3 2004-06-04 SPI42N03S2L-13 SPP42N03S2L-13 1 Power dissipation P tot=f(T C) 2 Drain current I D=f(T C); V GS10 V SPB42N03S2L-13 90 80 70 60 50 40 30 P tot [W] 40 30 20 10 0 0 50 100 150 200 I D [A] 20 10 0 0 50 100 150 200 50 T C [C] T C [C] 3 Safe operating area I D=f(V DS); T C=25 C; D =0 parameter: t p 103 1000 4 Max. transient thermal impedance Z thJC=f(t p) parameter: D =t p/T 101 10 limited by on-state resistance 1 s 100 10 s 1 0.5 102 100 0.2 Z thJC [K/W] 100 0.1 0.1 I D [A] 100 s 10-1 0.05 0.02 0.01 101 10 1 ms 10-2 0.01 single pulse 100 1 0.1 1 10 10-3 2 0.001 0 0 0 0 0 0 1 10 -1 10 0 V DS [V] 10 1 10 10 -6 10 -5 10 -4 t p [s] 10 -3 10 -2 10 -1 100 Rev. 2.0 page 4 2004-06-04 SPI42N03S2L-13 SPP42N03S2L-13 5 Typ. output characteristics I D=f(V DS); T j=25 C parameter: V GS 120 10 V 6V 5.5 V 5V SPB42N03S2L-13 6 Typ. drain-source on resistance R DS(on)=f(I D); T j=25 C parameter: V GS 40 3V 3.5 V 4V 100 30 80 R DS(on) [m] 4.5 V I D [A] 60 4V 20 4.5 V 5V 5.5 V 6V 10 V 40 10 3.5 V 20 3V 0 0 1 2 3 4 5 0 0 10 20 30 40 50 60 V DS [V] I D [A] 7 Typ. transfer characteristics I D=f(V GS); |V DS|>2|I D|R DS(on)max parameter: T j 100 90 80 70 60 50 40 30 20 175 C 8 Typ. forward transconductance g fs=f(I D); T j=25 C 60 50 40 g fs [S] 25 C I D [A] 30 20 10 10 0 0 1 2 3 0 4 5 0 20 40 60 80 V GS [V] I D [A] Rev. 2.0 page 5 2004-06-04 SPI42N03S2L-13 SPP42N03S2L-13 9 Drain-source on-state resistance R DS(on)=f(T j); I D=21 A; V GS=10 V 10 Typ. gate threshold voltage V GS(th)=f(T j); V GS=V DS parameter: I D 30 2.5 SPB42N03S2L-13 25 2 20 800 A R DS(on) [m] V GS(th) [V] 1.5 37 A 15 98 % typ 1 10 5 0.5 0 -60 -20 20 60 100 140 180 0 -60 -20 20 60 100 140 180 T j [C] T j [C] 11 Typ. capacitances C =f(V DS); V GS=0 V; f =1 MHz 12 Forward characteristics of reverse diode I F=f(V SD) parameter: T j 10000 104 1000 25C 98% 1000 103 Ciss 100 175 C 175C 98% 25 C Coss C [pF] Crss 100 102 I F [A] 10 10 0 5 10 15 20 25 30 1 0.0 0.5 1.0 1.5 2.0 2.5 3.0 V DS [V] V SD [V] Rev. 2.0 page 6 2004-06-04 SPI42N03S2L-13 SPP42N03S2L-13 13 Avalanche characteristics E AS=f(Tj) parameter: ID=42A, VDD=25V, RGS=25 120 SPB42N03S2L-13 14 Typ. gate charge V GS=f(Q gate); I D=21 A pulsed parameter: V DD 16 6V 14 100 12 80 10 24 V E AS [mJ] 60 V GS [V] 8 6 40 4 20 2 0 25 50 75 100 125 150 175 0 0 4 8 12 16 20 24 28 32 36 T j [C] Q gate [nC] 15 Drain-source breakdown voltage V BR(DSS)=f(T j); I D=1 mA 16 Gate charge waveforms 35 V GS 34 33 32 Qg V BR(DSS) [V] 31 30 29 28 27 -60 -20 20 60 100 140 180 V g s(th) Q g (th) Q gs Q sw Q gd Q gate T j [C] Rev. 2.0 page 7 2004-06-04 SPI42N03S2L-13 SPP42N03S2L-13 Package Outline P-TO263-3-2: Outline Footprint SPB42N03S2L-13 Packaging P-TO262-3-1: Outline Dimensions in mm Rev. 2.0 page 8 2004-06-04 SPI42N03S2L-13 SPP42N03S2L-13 Package Outline P-TO220-3-1: Outline SPB42N03S2L-13 Packaging Dimensions in mm Rev. 2.0 page 9 2004-06-04 SPI42N03S2L-13 SPP42N03S2L-13 Published by Infineon Technologies AG Bereich Kommunikation St.-Martin-Strae 53 D-81541 Munchen (c) Infineon Technologies AG 1999 All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices, please contact your nearest Infineon Technologies office in Germany or our Infineon Technologies representatives worldwide (see address list). Warnings Due to technical requirements, components may contain dangerous substances. For information on the types in question, please contact your nearest Infineon Technologies office. Infineon Technologies' components may only be used in life-support devices or systems with the expressed written approval of Infineon Technologies if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered. Further information Please note that the part number is BSPP42N03S2L-13, BSPB42N03S2L-13 and BSPI42N03S2L, for simplicity the device is refered to by the term SPP42N03S2L-13, SPB42N03S2L-13, SPI42N03S2L-13 throughout this documentation. SPB42N03S2L-13 Rev. 2.0 page 10 2004-06-04 |
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